[Battlemesh] Atheros chips [was: 802.11ac improvements]
Ferry Huberts
mailings at hupie.com
Fri Feb 26 01:11:13 UTC 2016
On 26/02/16 01:43, Juliusz Chroboczek wrote:
>> https://wikidevi.com/wiki/Qualcomm_Atheros
>
> Thanks, interesting link.
>
> Could somebody who understands this stuff explain the logic behind their
> SoC cores? The .11n design use single-core 24K and 74K MIPS chips, while
> the single .11ac design uses quad-core Cortex-A7.
Usual answer: cost cost cost
Normal tactics are: fast design that is 'a bit more expensive than
perhaps wanted' to grab market share, then do a cost reduction to
actually make some money.
I was in SoC design and cost was basically the only thing that _really_
mattered.
Just look at some products: v1 is perhaps ARM and v2 suddenly is MIPS
(as an example) in the _same_ product.
Technically completely different, but marketing wise the same.
>
> Why the switch to ARM, and why the quad-core Cortex-A7 instead of
> a single- or dual-core Cortex-A9, which would probably give better
> performance with a simpler design?
>
> (I know, I know, I'm an old man and don't get this multi-core goodness.)
>
> -- Juliusz
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--
Ferry Huberts
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