[Battlemesh] Atheros chips

Jonathan Morton chromatix99 at gmail.com
Fri Feb 26 08:16:33 CET 2016

> On 26 Feb, 2016, at 03:39, Juliusz Chroboczek <jch at pps.univ-paris-diderot.fr> wrote:
> And why would Atheros use a quad-core A7 instead of a single-core A9?

The A7 is a newer design (despite the number - the A8 is the oldest in the Cortex-A family, and the A9 is the second oldest) and considerably smaller for almost the same performance per core.  ARM’s numbering scheme is a little obscure, but in the <20 range, it roughly corresponds to the relative die area of ARMv7 cores, not its performance.  The >20 range is reserved for ARMv8 cores.

The reason for the smallness is that the A7 is an in-order design whereas A9 is out-of-order (both are dual-issue).  Additionally, being newer, the A7 cleared out some important bottlenecks in the memory subsystem.

When you can target a single core type, the difference between in-order and OoO is much less important than on the desktop, where the CPU must cope with whatever crap gets thrown at it.

I believe that’s also why the Raspberry Pi 2 uses quad A7s.  Next to the fairly substantial GPU in its BCM SoC, the difference in size between a quad A7 and the old single ARM11 core is relatively small.

The use of multiple A-series cores indicates that size was not the only consideration - there was also a minimum performance standard to be met.  The cheapest ARM core available is the Cortex-M0, which is specifically designed to be tiny and cheap above all else.  I believe it’s less than half the transistor count of the smallest 68K core, but still with many times the performance.

 - Jonathan Morton

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